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| TS4851 MONO 1 W SPEAKER AND STEREO 160 mW HEADSET BTL DRIVERS WITH DIGITAL VOLUME CONTROL s s s s s s s s s s s s s Operating from VCC = 3 V to 5.5 V Rail to rail input/output Speaker driver with 1 W output @ Vcc = 5 V, THD+N = 1%, F = 1 kHz, 8 load Headset drivers with 160 mW output @ Vcc = 5 V, THD+N = 1%, F = 1 kHz, 32 load Headset output is 30 mW in stereo @ Vcc = 3 V THD+N < 0.5% Max @ 20 mW into 32 BTL, 50 Hz < Frequency < 20 kHz 32-step digital volume control from 34.5 dB to +12 dB +6 dB power up volume and full standby 8 different output modes Pop & click reduction circuitry Low shutdown current (< 100 nA) Thermal shutdown protection Flip-chip package 18 x 300 m bumps PIN CONNECTIONS (top view) TS485IJT - Flip Chip DESCRIPTION The TS4851 is a low power audio amplifier that can drive either both a mono speaker or a stereo headset. To the speaker, it can deliver 400 mW (typ.) of continuous RMS output power into an 8 load with a 1% THD+N value. To the headset driver, the amplifier can deliver 30 mW (typ.) per channel of continuous average power into a stereo 32 bridged-tied load with 0.5% THD+N @ 3.3 V. This device features a 32-step digital volume control and 8 different output selections. The digital volume and output modes are controlled through a three-digit SPI interface bus. R OUT< R OUT + R IN L IN PHONE IN SPKR OUT+ BYPASS GND VCC SPKR OUT CLK VCC Pin Out (top view) GND L OUT + L OUT - DATA APPLICATIONS s Mobile Phones ORDER CODE Package Part Number TS4851IJT Temperature Range J -40, +85C * NC ENB J = Flip Chip Package - only available in Tape & Reel (JT)) April 2003 Revision B 1/26 TS4851 1 Application Information for a Typical Application APPLICATION INFORMATION FOR A TYPICAL APPLICATION External component descriptions Component Cin Functional Description This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the amplifier's input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc =1/ (2i x Zin x Cin). This is the Supply Bypass capacitor. It provides power supply filtering. This is the Bypass pin capacitor. It provides half-supply filtering. Cs CB 2/26 SPI Bus Interface 2 SPI BUS INTERFACE TS4851 2.1 Pin descriptions Pin DATA CLK ENB This is the serial data input pin. This is the clock input pin. This is the SPI enable pin active at high level. Functional Description 2.2 Description of SPI operation The serial data bits are organized into a field containing 8 bits of data as shown in Table 1. The DATA 0 to DATA 2 bits determine the output mode of the TS4851 as shown in Table 2. The DATA 3 to DATA 7 bits determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored after the height rising clock edge has occurred. For any data sequence longer than 8 bits, only the first 8 bits will get loaded into the shift register and the rest of the bits will be disregarded. Table 1: Bit Allocation DATA LSB DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 MSB DATA 7 MODES Mode 1 Mode 2 Mode 3 gain 1 gain 2 gain 3 gain 4 gain 5 Table 2: Output mode selection: G from -34.5 dB to +12 dB (by steps of 1.5 dB) Output Mode # 0 1 2 3 4 5 DATA 2 0 0 0 0 1 1 DATA 1 0 0 1 1 0 0 DATA 0 0 1 0 1 0 1 SPKERout1 SD 6dBxP SD Gx(R+L) SD Gx(R+L) +6dBxP Rout SD SD 0dBxP SD GxR SD Lout SD SD 0dBxP SD GxL SD 6 7 1) 1 1 1 1 0 1 SD 6dBxP GxR+0dBxP GxR+0dBxP GxL+0dBxP GxL+0dBxP SD = Shutdown Mode, P = Phone in Input, R = Rin input and L = Lin input 3/26 TS4851 Table 3: Volume Control Settings K : Gain (dB) -34.5 -33.0 -31.5 -30.0 -28.5 -27.0 -25.5 -24.0 -22.5 -21.0 -19.5 -18.0 -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 0.0 1.5 3.0 4.5 6 7.5 9 10.5 12 DATA 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA 6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DATA 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DATA 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SPI Bus Interface DATA 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 4/26 SPI Bus Interface 2.3 SPI Timing Diagram TS4851 5/26 TS4851 3 ABSOLUTE MAXIMUM RATINGS Symbol VCC Toper Tstg Tj Rthja Pd ESD ESD Absolute Maximum Ratings Parameter Supply voltage1 Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Flip Chip Thermal Resistance Junction to Ambient2 Power Dissipation Human Body Model Machine Model Latch-up Immunity Lead Temperature (soldering, 10sec) Value 6 -40 to + 85 -65 to +150 150 200 Internally Limited 2 100 200 250 Unit V C C C C/W kV V mA C 1) 2) All voltages values are measured with respect to the ground pin. Device is protected in case of over temperature by a thermal shutdown active @ 150C 4 OPERATING CONDITIONS Symbol VCC Vphin VRin/VLin TSD Rthja Supply Voltage Maximum Phone In Input Voltage Maximum Rin & Lin Input Voltage Thermal Shut Down Temperature Flip Chip Thermal Resistance Junction to Ambient1 Parameter Value 3 to 5.5 GND to VCC GND to VCC 150 90 Unit V V V C C/W 1) Device is protected in case of over temperature by a thermal shutdown active @ 150C 6/26 Electrical Characteristics 5 ELECTRICAL CHARACTERISTICS TS4851 Table 4: Electrical characteristics at VCC = +5 V, GND = 0 V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current Output Mode 7, Vin = 0 V, no load All other output modes, Vin = 0 V, no load Standby Current Output Mode 0 Output Offset Voltage (differential) Vin = 0 V "Logic low" input Voltage "Logic high" input Voltage Output Power SPKERout, RL = 8 , THD = 1%, F = 1 kHz Rout & Lout, RL = 32 , THD = 0.5%, F = 1 kHz Total Harmonic Distortion + Noise Rout & Lout, Po = 80 mW, F = 1 kHz, RL = 32 SPKERout, Po = 800 mW, F = 1 kHz, RL = 8 Rout & Lout, Po = 50 mW, 20 Hz < F < 20 kHz, RL = 32 SPKERout, Po = 40 mW, 20 Hz < F < 20 kHz, RL = 8 Signal To Noise Ratio (A-Weighted) Power Supply Rejection Ratio (Output Mode = 2)2 Vripple = 200 mV Vpp, F = 217 Hz, Input Floating Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 10 Digital Gain Range - Rin & Lin no load Digital gain stepsize Stepsize G -22.5 dB G < -22.5 dB Phone In Gain, no load BTL gain from Phone In to SPKERout BTL gain from Phone In to Rout & Lout Zin Zin tes teh tel tds tdh tcs tch tcl fclk 1) 2) Min. Typ. 8 4.5 0.1 5 Max. 11 6.5 Unit mA ISTANDBY Voo Vil Vih Po A 2 mV 50 0.4 5 1000 120 % 0.5 1 0.5 1 90 61 62 dB -34.5 1.5 -0.5 -1 6 0 15 37.5 20 20 30 20 20 20 50 50 DC 10 20 50 25 62.5 k k ns ns ns ns ns ns ns ns MHz +0.5 +1 dB +12 dB dB dB dB V V mW 800 80 0 1.4 THD + N SNR PSRR1 G Phone In Input Impedance Rin & Lin Input Impedance (all gain setting) Enable Stepup Time - ENB Enable Hold Time - ENB Enable Low Time - ENB Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK All PSRR data limits are guaranted by evaluation desgin test. Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217 Hz 7/26 TS4851 Electrical Characteristics Table 5: Electrical characteristics at VCC = +3.0V, GND = 0V, Tamb = 25C (unless otherwise specified) Symbol ICC Parameter Supply Current Output Mode 7, Vin = 0 V,no load All other output modes, Vin = 0 V,no load Standby Current Output Mode 0 Output Offset Voltage (differential) Vin = 0 V "Logic low" input Voltage "Logic high" input Voltage Output Power SPKERout, RL = 8 , THD = 1%, F = 1 kHz Rout & Lout, RL = 32 , THD = 0.5%, F = 1 kHz Total Harmonic Distortion + Noise Rout & Lout, Po = 20 mW, F = 1 kHz, RL = 32 SPKERout, Po = 300 mW, F = 1 kHz, RL = 8 Rout & Lout, Po = 15 mW, 20 Hz < F < 20 kHz, RL = 32 SPKERout, Po = 250 mW, 20 Hz < F < 20 kHz, RL = 8 Signal To Noise Ratio (A-Weighted) Power Supply Rejection Ratio (Output Mode = 2)2 Vripple = 200 mV Vpp, F = 217 Hz, Input Floating Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 10 Digital Gain Range - Rin & Lin no load Digital gain stepsize Stepsize error G -22.5 dB G < -22.5 dB Phone In Gain, no load BTL gain from Phone In to SPKERout BTL gain from Phone In to Rout & Lout Min. Typ. 7.5 4.5 0.1 5 Max. 10 6.5 Unit mA ISTANDBY Voo Vil Vih Po A 2 mV 50 0.4 5 340 30 % 0.5 1 0.5 1 86 61 62 dB -34.5 1.5 -0.5 -1 6 0 15 37.5 20 20 30 20 20 20 50 50 DC 10 20 50 25 62.5 k k ns ns ns ns ns ns ns ns MHz +0.5 +1 dB +12 dB dB dB dB V V mW 300 20 0 1.4 THD + N SNR PSRR1 G Zin Zin tes teh tel tds tdh tcs tch tcl fclk 1) 2) Phone In Input Impedance 1 Rin & Lin Input Impedance (All Gain Setting) 1 Enable Stepup Time - ENB Enable Hold Time - ENB Enable Low Time - ENB Data Setup Time- DATA Data Hold Time - DATA Clock Setup time - CLK Clock Logic High Time - CLK Clock Logic Low Time - CLK Clock Frequency - CLK All PSRR data limits are guaranted by evaluation desgin test. Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217 Hz. 8/26 Electrical Characteristics Index of Graphics Description THD + N vs. Output Power THD + N vs. Frequency Output Power vs. Power Supply Voltage PSRR vs. Frequency Frequency Response Signal to Noise Ratio vs. Power Supply Voltage Crosstalk vs. Frequency -3 dB Lower Cut Off Frequency vs. Input Capacitor Current Consumption vs. Power Supply Voltage Power Dissipation vs. Output Power Power Derating Curves -3 dB Lower Cut Off Frequency vs. Gain Setting TS4851 Figure Figures 1 to 10 Figures 11 to 20 Figures 21 to 28 Figures 29 to 38 Figures 39 to 42 Figures 43 to 46 Figures 47 to 48 Figures 49 to 50 Figure 51 Figures 52 to 55 Figure 56 Figure 57 Page page 10 to page 11 page 11 to page 13 page 13 to page 14 page 14 to page 16 page 16 page 17 page 18 page 18 page 18 page 18 to page 19 page 19 page 19 Note: In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used. All measurements made with Cin = 220 nF, Cb = Cs = 1 F except in PSRR condition where Cs = 0. 9/26 TS4851 Figure 1: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 4 Out. Mode = 1, 7 Vcc=3V BW < 125kHz F=20kHz Tamb = 25C THD + N (%) Electrical Characteristics Figure 4: HDout THD+N vs. output power (output mode 2) 10 Vcc=5V F=20kHz THD + N (%) RL = 16 Out. Mode = 2 BW < 125kHz Tamb = 25C 1 Vcc=5V F=20kHz Vcc=3V F=20kHz 1 0.1 Vcc=3V F=1kHz 0.1 Vcc=3V F=1kHz 1E-3 0.01 0.1 Output Power (W) Vcc=5V F=1kHz 1 0.01 1E-3 Vcc=5V F=1kHz 0.01 0.1 Output Power (W) Figure 2: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 8 Out. Mode = 1, 7 BW < 125kHz Tamb = 25C THD + N (%) Figure 5: HDout THD+N vs. output power (output mode 2) 10 Vcc=3V F=20kHz Vcc=5V F=20kHz THD + N (%) 1 RL = 32 Out. Mode = 2 BW < 125kHz Tamb = 25C Vcc=5V F=20kHz Vcc=3V F=20kHz 1 Vcc=3V F=1kHz 0.1 Vcc=3V F=1kHz 0.1 Vcc=5V F=1kHz 0.01 Vcc=5V F=1kHz 0.01 Output Power (W) 0.1 1E-3 0.01 0.1 Output Power (W) 1 1E-3 Figure 3: Spkout THD+N vs. output power (output modes 1, 7) 10 RL = 16 Out. Mode = 1, 7 BW < 125kHz Tamb = 25C THD + N (%) Figure 6: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 Vcc=5V F=20kHz THD + N (%) 1 Vcc=3V F=20kHz RL = 4 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=3V F=20kHz Vcc=5V F=20kHz 0.1 Vcc=3V F=1kHz 0.01 1E-3 Vcc=5V F=1kHz Vcc=5V F=1kHz 1 0.1 1E-3 Vcc=3V F=1kHz 0.01 0.1 Output Power (W) 1 0.01 0.1 Output Power (W) 10/26 Electrical Characteristics Figure 7: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 RL = 8 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=5V F=20kHz THD + N (%) TS4851 Figure 10: HDout THD+N vs. output power (output mode 4, G=+12dB) 10 RL = 32 Out. Mode = 4 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=5V F=20kHz Vcc=3V F=20kHz THD + N (%) Vcc=3V F=20kHz 0.1 Vcc=3V F=1kHz 1E-3 0.01 0.1 Output Power (W) Vcc=5V F=1kHz 1 0.1 Vcc=3V F=1kHz 1E-3 0.01 0.1 Output Power (W) Vcc=5V F=1kHz Figure 8: Spkout THD+N vs. output power (output mode 3, G=+12dB) 10 RL = 16 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=5V F=20kHz Figure 11: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 4 Out. Mode = 1, 7 BW < 125kHz Tamb = 25C THD + N (%) THD + N (%) Vcc=3V F=20kHz 1 Vcc=3V P=450mW Vcc=5V P=1.1W Vcc=3V F=1kHz 0.1 Vcc=5V F=1kHz 1E-3 0.01 0.1 Output Power (W) 1 0.1 0.01 20 100 1000 Frequency (Hz) 10000 20k Figure 9: HDout THD+N vs. output power (output mode 4, G=+12dB) 10 RL = 16 Out. Mode = 4 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=5V F=20kHz Figure 12: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 8 Out. Mode = 1, 7 BW < 125kHz Tamb = 25C THD + N (%) THD + N (%) Vcc=3V F=20kHz 1 Vcc=3V P=350mW Vcc=5V P=0.8W 0.1 0.1 Vcc=3V F=1kHz 1E-3 0.01 0.1 Output Power (W) Vcc=5V F=1kHz 0.01 20 100 1000 Frequency (Hz) 10000 20k 11/26 TS4851 Figure 13: Spkout THD+N vs. frequency (output modes 1, 7) 10 RL = 16 Out. Mode = 1, 7 BW < 125kHz Tamb = 25C THD + N (%) Electrical Characteristics Figure 16: Spkout THD+N vs.frequency (output mode 3, G = +12 dB) 10 RL = 4 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=3V P=180mW 0.1 THD + N (%) 1 Vcc=5V P=0.55W Vcc=5V P=1.1W 0.1 0.01 20 10000 20k 20 Vcc=3V P=450mW 100 1000 Frequency (Hz) 10000 20k 100 1000 Frequency (Hz) Figure 14: HDout THD+N vs. frequency (output mode 2) 10 RL = 16 Out. Mode = 2 BW < 125kHz Tamb = 25C THD + N (%) Figure 17: Spkout THD+N vs. frequency (output mode 3, G = +12 dB) 10 RL = 8 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=3V P=40mW 0.1 Vcc=5V P=220mW 0.01 20 100 1000 Frequency (Hz) 10000 20k THD + N (%) 1 Vcc=3V P=350mW 0.1 20 Vcc=5V P=0.8W 100 1000 Frequency (Hz) 10000 20k Figure 15: HDout THD+N vs. frequency (output mode 2) 10 RL = 32 Out. Mode = 2 BW < 125kHz Tamb = 25C THD + N (%) Figure 18: Spkout THD+N vs. frequency (output mode 3, G = +12 dB) 10 RL = 16 Out. Mode = 3 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=3V P=20mW 0.1 Vcc=5V P=100mW 0.01 20 100 1000 Frequency (Hz) 10000 20k THD + N (%) 1 Vcc=5V P=0.55W 0.1 20 Vcc=3V P=180mW 100 1000 Frequency (Hz) 10000 20k 12/26 Electrical Characteristics Figure 19: HDout THD+N vs. frequency (output mode 4, G = +12 dB) 10 Output power at 10% THD + N (W) TS4851 Figure 22: Speaker output power vs. power supply voltage (output mode 1, 7) 2.4 THD + N (%) RL = 16 Out. Mode = 4 G = +12dB BW < 125kHz Tamb = 25C 1 Vcc=3V P=40mW F = 1kHz Output Mode = 1, 7 2.0 BW < 125kHz Tamb = 25C 1.6 1.2 0.8 0.4 8 4 16 0.1 20 Vcc=5V P=220mW 100 1000 Frequency (Hz) 10000 20k 32 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 Figure 20: HDout THD+N vs. frequency (output mode 4, G = +12 dB) 10 Figure 23: Headphone output power vs. load resistor (output mode 2) 350 Output power at 1% THD + N (mW) F = 1kHz 300 Output Mode = 2 BW < 125kHz Tamb = 25C 250 200 150 100 50 64 0 3.0 3.5 4.0 4.5 Vcc (V) 5.0 5.5 THD + N (%) RL = 32 Out. Mode = 4 G = +12dB BW < 125kHz 1 Tamb = 25C Vcc=3V P=20mW 16 32 0.1 Vcc=5V P=100mW 0.01 20 100 1000 Frequency (Hz) 10000 20k Figure 21: Speaker output power vs. power supply voltage (output mode 1, 7) 2.0 Output power at 1% THD + N (W) Figure 24: Headphone output power vs. load resistor (output mode 2) 400 4 8 Output power at 10% THD + N (mW) F = 1kHz Output Mode = 1, 7 1.6 BW < 125kHz Tamb = 25C 1.2 F = 1kHz 350 Output Mode = 2 BW < 125kHz 300 Tamb = 25C 250 200 150 100 50 0 3.0 3.5 4.0 16 32 0.8 16 0.4 32 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 64 4.5 Vcc (V) 5.0 5.5 13/26 TS4851 Figure 25: Speaker output power vs. power supply voltage (output mode 3) 2.0 8 4 Output power at 10% THD + N (mW) Output power at 1% THD + N (W) Electrical Characteristics Figure 28: Headphone output power vs. load resistance (output mode 2) 400 F = 1kHz 350 Output Mode = 4 BW < 125kHz 300 Tamb = 25C 250 200 150 100 50 0 3.0 3.5 4.0 4.5 Vcc (V) 5.0 5.5 64 32 F = 1kHz Output Mode = 3 1.6 BW < 125kHz Tamb = 25C 1.2 16 0.8 16 0.4 32 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 Figure 26: Speaker output power vs. power supply voltage (output mode 3) 2.4 Output power at 10% THD + N (W) Figure 29: Spkout PSRR vs. frequency (output modes 1, 7, input grounded) 0 F = 1kHz Output Mode = 3 2.0 BW < 125kHz Tamb = 25C 1.6 1.2 0.8 8 4 -10 -20 PSRR (dB) Ouput mode 1, 7 RL = 8 Vripple=0.2Vpp BW < 125kHz Tamb = 25C -30 -40 -50 Vcc=3V 16 0.4 32 0.0 3.0 3.5 4.0 Vcc (V) 4.5 5.0 5.5 -60 Vcc=5V -70 100 1000 10000 Frequency (Hz) 100000 Figure 27: Headphone output power vs. load resistor (output mode 4) 350 Figure 30: HDout PSRR vs. frequency (output mode 2, input grounded) 0 -10 Ouput mode 2 RL = 32 Vripple=0.2Vpp BW < 125kHz Tamb = 25C Output power at 1% THD + N (mW) F = 1kHz 300 Output Mode = 4 BW < 125kHz Tamb = 25C 250 200 150 100 50 0 3.0 16 -20 PSRR (dB) -30 -40 -50 Vcc=3V & 5V 32 64 -60 -70 3.5 4.0 4.5 Vcc (V) 5.0 5.5 100 1000 10000 Frequency (Hz) 100000 14/26 Electrical Characteristics Figure 31: Spkout PSRR vs. frequency (output mode 3, inputs grounded) 0 Output mode 3 Vcc=+5V RL = 8 Vripple=0.2Vpp BW < 125kHz Tamb = 25C G=+6dB G=+12dB G=+9dB PSRR (dB) TS4851 Figure 34: HDout PSRR vs. frequency (output mode 4, inputs grounded) 0 Output mode 4 -10 Vcc=+3V RL = 32 Vripple=0.2Vpp -20 BW < 125kHz Tamb = 25C -30 G=-12dB -40 G=0dB G=-34.5dB 100 1000 10000 Frequency (Hz) 100000 -10 G=+6dB G=+12dB G=+9dB PSRR (dB) -20 -30 G=-12dB G=0dB -40 -50 100 G=-34.5dB 1000 10000 Frequency (Hz) 100000 -50 Figure 32: Spkout PSRR vs. frequency (output mode 3, inputs grounded) 0 Output mode 3 Vcc=+3V RL = 8 Vripple=0.2Vpp BW < 125kHz Tamb = 25C G=+6dB G=+12dB G=+9dB Figure 35: Spkout PSRR vs. frequency (output mode 5, inputs grounded) 0 Output mode 5 Vcc=+5V RL = 8 Vripple=0.2Vpp -20 BW < 125kHz Tamb = 25C -10 -30 G=+6dB G=+12dB G=+9dB -10 PSRR (dB) -30 G=-12dB G=0dB PSRR (dB) -20 G=-12dB G=0dB -40 -40 G=-34.5dB -50 100 G=-34.5dB 1000 10000 Frequency (Hz) 100000 -50 100 1000 10000 Frequency (Hz) 100000 Figure 33: HDout PSRR vs. frequency (output mode 4, inputs grounded) 0 Output mode 4 Vcc=+5V RL = 32 Vripple=0.2Vpp BW < 125kHz Tamb = 25C Figure 36: Spkout PSRR vs. frequency (output mode 5, inputs grounded) 0 Output mode 5 Vcc=+3V RL = 8 Vripple=0.2Vpp -20 BW < 125kHz Tamb = 25C -10 -30 G=+6dB G=+12dB G=+9dB -10 G=+6dB G=+12dB G=+9dB PSRR (dB) PSRR (dB) -20 -30 G=-12dB -40 G=0dB G=-34.5dB 100 1000 10000 Frequency (Hz) 100000 G=-12dB G=0dB -40 G=-34.5dB -50 -50 100 1000 10000 Frequency (Hz) 100000 15/26 TS4851 Figure 37: HDout PSRR vs. frequency (output modes 6, 7, inputs grounded) 0 Output mode 6, 7 Vcc=+5V RL = 32 Vripple=0.2Vpp BW < 125kHz Tamb = 25C Electrical Characteristics Figure 40: HDout frequency response (output mode 2) 0 -10 G=+6dB G=+12dB G=+9dB Output level (dB) -2 Vcc=5V Vcc=3V -4 Ouput mode 2 RL = 32 Cin=220nF BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 PSRR (dB) -20 -30 G=-12dB -40 G=0dB G=-34.5dB 100 1000 10000 Frequency (Hz) 100000 -6 -50 20 Figure 38: HDout PSRR vs. freq., (output modes 6, 7, inputs grounded) 0 Output mode 6, 7 Vcc=+3V RL = 32 Vripple=0.2Vpp BW < 125kHz Tamb = 25C Figure 41: Spkout frequency response (output mode 3) 12 10 Output level (dB) -10 G=+6dB G=+12dB G=+9dB Vcc=5V Vcc=3V PSRR (dB) -20 8 6 4 2 Ouput mode 3 RL = 8 G = +12dB Cin=220nF BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 -30 G=-12dB -40 G=0dB G=-34.5dB 100 1000 10000 Frequency (Hz) 100000 -50 0 20 Figure 39: Spkout frequency response (output mode 1, 7) 6 Figure 42: HDout frequency response (output mode 4) 12 10 Vcc=3V Vcc=5V Output level (dB) Output level (dB) 4 Vcc=3V Vcc=5V 8 6 4 2 0 20 Ouput mode 4 RL = 32 G = +12dB Cin=220nF BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 2 Ouput mode 1, 7 RL = 8 Cin=220nF BW < 125kHz Tamb = 25C 100 1000 Frequency (Hz) 10000 0 20 16/26 Electrical Characteristics Figure 43: Spkout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz TS4851 Figure 45: HDout SNR vs. power supply voltage, unweighted filter, BW = 20 Hz to 20 kHz ohms ohms ohms Figure 44: Spkout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz Figure 46: HDout SNR vs. power supply voltage, weighted filter A, BW = 20 Hz to 20 kHz ohms ohms 17/26 TS4851 Figure 47: Crosstalk vs. frequency (output mode 4) 0 Ouput mode 4 Vcc = 5V RL = 32 G = +12dB Pout = 100mW BW < 125kHz Tamb = 25C Lower -3dB Cut Off Frequency (Hz) Electrical Characteristics Figure 50: -3 dB lower cut off frequency vs. input capacitance Rin & Lin Inputs All gain setting Tamb=25C Crosstalk Level (dB) -20 10 -40 Lout -> Rout Rout -> Lout Typical Input Impedance Minimum Input Impedance Maximum Input Impedance -60 -80 20 100 1000 Frequency (Hz) 10000 1 0.1 Input Capacitor (F) 1 Figure 48: Crosstalk vs. frequency (output mode 4) 0 Ouput mode 4 Vcc = 3V RL = 32 G = +12dB Pout = 20mW BW < 125kHz Tamb = 25C Figure 51: Current consumption vs. power supply voltage 10 No loads 9 Tamb = 25 C 8 7 Icc (mA) 6 5 4 3 2 Mode 7 Crosstalk Level (dB) -20 Mode 2, 4, 6 -40 Rout -> Lout Lout -> Rout -60 -80 20 100 1000 Frequency (Hz) 10000 1 0 0 1 2 Vcc (V) 3 Mode 1, 3, 5 4 5 Figure 49: -3 dB lower cut off frequency vs. input capacitor 100 Lower -3dB Cut Off Frequency (Hz) Phone In Input Tamb=25C Figure 52: Power dissipation vs. output power (speaker output) 1.4 Vcc=5V 1.2 F=1kHz THD+N<1% 1.0 0.8 0.6 0.4 0.2 RL=16 0.0 0.0 RL=8 Typical Input Impedance Minimum Input Impedance 10 Maximum Input Impedance 1 Input Capacitor ( F) 0.1 Power Dissipation (W) RL=4 0.2 0.4 0.6 0.8 1.0 1.2 Output Power (W) 1.4 1.6 18/26 Electrical Characteristics Figure 53: Power dissipation vs. output power (speaker output) 0.5 Vcc=3V F=1kHz 0.4 THD+N<1% Power Dissipation (W) TS4851 Figure 56: Power derating curves 100 Lower -3dB Cut Off Frequency (Hz) Rin & Lin Inputs Input Impedance is Nominal Tamb=25C Cin=100nF RL=4 Cin=220nF 0.3 10 0.2 RL=8 0.1 RL=16 0.0 0.0 0.1 0.2 0.3 0.4 0.5 Cin=1F Cin=470nF 1 -34.5 -20 Gain Setting (dB) 0 12 Output Power (W) Figure 54: Power dissipation vs. output power (headphone output, one channel) 0.4 Vcc=5V F=1kHz THD+N<1% 0.3 Figure 57: -3 dB lower cut off frequency vs. gain setting (output modes 3, 4, 5, 6, 7) Flip-Chip Package Power Dissipation (W) 1.4 1.2 1.0 0.8 0.6 0.4 No Heat sink 0.2 0.0 Heat sink surface = 125mm 2 Power Dissipation (W) 0.2 RL=16 0.1 RL=32 0.0 0.00 0.05 0.10 0.15 0.20 Output Power (W) 0.25 0 25 50 75 100 125 150 Ambiant Temperature ( C) Figure 55: Power dissipation vs. output power (headphone output one channel) 120 Vcc=3V F=1kHz 100 THD+N<1% 80 60 RL=16 Table 6: Output noise (all inputs grounded) Output Mode 1 2 3 Unweighted Filter from 3V to 5V 23Vrms 20Vrms 70vVrms 53Vrms 79Vrms 60Vrms Weighted Filter (A) from 3V to 5V 20Vrms 17Vrms 60Vrms 45Vrms 67Vrms 51vVrms Power Dissipation (mW) 40 RL=32 20 4 5 0 0 10 20 30 40 50 Output Power (mW) 60 70 6 19/26 TS4851 6 APPLICATION INFORMATION Application Information 6.1 BTL configuration principles The TS4851 integrates 3 monolithic power amplifier having BTL output. BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single ended output 1 = Vout1 = Vout (V) Single ended output 2 = Vout2 = -Vout (V) and Vout1 - Vout2 = 2Vout (V) The output power is: Pout = ( 2 Vout RMS ) 2 (W ) RL Then, the power dissipated by each amplifier is Pdiss = Psupply - Pout (W) Pdiss = 2 2 VCC RL POUT - POUT (W ) and the maximum value is obtained when: Pdiss --------------------- = 0 POUT and its value is: Pdiss max = Note: 2 Vcc 2 2RL (W) This maximum value is depends only on power supply voltage and load values. For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration. The efficiency is the ratio between the output power and the power supply: VPEAK POUT = ----------------------- = ---------------------Psup ply 4VCC The maximum theoretical value is reached when Vpeak = Vcc, so: ---- = 78.5% 4 The TS4851 has three independent power amplifiers. Each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of each amplifier's maximum power dissipation. It is calculated as follows: l Pdiss speaker = Power dissipation due to the 6.2 Power dissipation and efficiency Hypotheses: l Voltage and current in the load are sinusoidal (Vout and Iout). l Supply voltage is a pure DC source (Vcc). Regarding the load we have: VOUT = V PEAK sin t (V) and VOUT IOUT = ---------------- (A) RL and VPEAK 2 POUT = ---------------------- (W) 2RL Then, the average current delivered by the supply voltage is: ICC AVG speaker power amplifier. l Pdiss head = Power dissipation due to the Headphone power amplifier l Total Pdiss = Pdiss speaker + Pdiss head1 + Pdiss head2 (W) In most cases, Pdiss head1 = Pdiss head2, giving: Total P diss = Pdiss speaker + 2Pdiss head (W) TotalP diss = 2 2 VCC POUT SPEAKER POUT HEAD +2 R L HEAD R L SPEAKER - POUT SPEAKER + 2 POUT HEAD (W ) VPEA K = 2 ------------------- (A) RL The power delivered by the supply voltage is: Psupply = Vcc IccAVG (W) [ ] 20/26 Application Information The following graph (Figure 58) shows an example of the previous formula, with Vcc set to +5 V, Rload speaker set to 8 and Rload headphone set to 16 . Figure 58: Example of Total Power Dissipation vs. Speaker and Headphone Output Power TS4851 Cs has especially an influence on the THD+N in high frequency (above 7 kHz) and indirectly on the power supply disturbances. With 1 F, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than 1 F, THD+N increases in high frequency and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than 1 F, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency: * If Cb is lower than 1 F, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than 1 F, the benefit on THD+N and PSRR in the lower frequency range is small. * 6.3 Low frequency response In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3 dB cut off frequency. FCL = 1 (Hz ) 2 Zin Cin 6.5 Startup time When the TS4851 is controlled to switch from the full standby mode (output mode 0) to another output mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be calculated by the following formulas. Typical startup time = 0.0175 x Cb (s) Max. startup time = 0.025 x Cb (s) (Cb is in F in these formulas) These formulas assume that the Cb voltage is equal to 0 V. If the Cb voltage is not equal to 0V, the startup time will be always lower. The startup time is the delay between the negative edge of Enable input (see Description of SPI operation on page 3) and the power ON of the output amplifiers. Note: When the TS4851 is set in full standby mode, Cb is discharged through an internal resistor. The time to reach 0 V of Cb voltage could be calculated by the following formula: Zin is the input impedance of the corresponding input: * * 20 k for Phone In IHF input 50 k for the 3 other inputs For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off frequency doesn't change with gain setting. Note also that 20 k and 50 k are typical values and there are tolerances around these values (see Electrical Characteristics on page 7). Note: In Figures 39 to 41, you could easily establish the Cin value for a -3 dB cut-off frequency required. 6.4 Decoupling of the circuit Two capacitors are needed to bypass properly the TS4851, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. Note: Tdischarge = 3 x Cb (s) Cb must be in F in this formula. 21/26 TS4851 6.6 Pop and Click performance The TS4851 has internal Pop and Click reduction circuitry. The performance of this circuitry is closely linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb. The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N and PSRR requested always in lower frequency. The TS4851 is optimized to have a low pop and click in the typical schematic configuration (see page 2). Note: The value of Cs is not an important consideration as regards pop and click. Application Information * No bypass capacitor Cs is used. RMS PSRR = 20 x Log RMS Note: The PSRR value for each frequency is: ( Output ) ( Vripple ) ( dB ) The measure of the Rms voltage is not an Rms selective measure but a full range (20 Hz to 125 kHz) Rms measure. This means that the effective Rms signal + the Noise is measured. As the measurement is performed with a wideband frequency range apparatus, we have to subtract the Noise part (quadratic operation) of the measurement to obtain the real Rms signal needed to calculate the PSRR, as shown in the formula above. 6.7 Notes on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR? The PSSR was measured according to the schematic shown in Figure 59. Figure 59: PSRR measurement schematic Principles of operation * * The DC voltage supply (Vcc) is fixed. The AC sinusoidal ripple voltage (Vripple) is fixed. 22/26 Package Information 7 PACKAGE INFORMATION TS4851 Flip-chip - 18 bumps: TS4851JT Pin out (top view) 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN SPKR OUT + GND L OUT + L OUT - VCC DATA NC VCC ENB SPKR OUT - BYPASS GND CLK A B C D E Note: The solder bumps are on the underside. Marking (top view): The following markings are present on the topside of the flip-chip: l The ST logo. l The part number: A51. l A 3-digit date code: YWW. l A dot marking the location of Pin1A. A51 YWW 23/26 TS4851 TS4851 Footprint recommendation Package Information Package mechanical data 2440m Die size: 2170m x 2440m 30m Die height (including bumps): 600m 30m 2170m Bumps diameter: 300m 15m Bumps height: 250m 15m 750m 500m Pitch: 500m 10m 866m 866m 600m 24/26 Daisy Chain Samples 8 DAISY CHAIN SAMPLES TS4851 A daisy chain sample is a "dummy" silicon chip that can be used to test your flip-chip soldering process and connection continuity. The daisy chain sample features paired connections between bumps, as shown in the schematic below. On your PCB layout, you should design the bump connections such that they are complementary to the above schema (meaning that different pairs of bumps are connected on the PCB side). In this way, by simply connecting an ohmmeter between pin 1A and pin 5A, you can test the continuity of your soldering process. The order code for daisy chain samples is given below. Figure 60: Daisy chain sample mechanical data 2.44 mm 7 6 5 4 3 2 1 R OUTR OUT + R IN L IN PHONE IN SPKR OUT + GND L OUT L OUT + VCC DATA 2.17 mm NC VCC ENB SPKR OUT - BYPASS GND CLK A B C D E Order code for daisy chain samples Part Number TSDC02IJT Temperature Range -40, +85C Package Marking J * DC2 25/26 TS4851 9 TAPE & REEL SPECIFICATION Tape & Reel Specification Figure 61: Top view of tape and reel 1 1 A A User direction of feed Device orientation The devices are oriented in the carrier pocket with pin number 1A adjacent to the sprocket holes. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com 26/26 |
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